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SV51006
2014.01.10
Figure 5-23: LVPECL DC-Coupled Termination
LVPECL
Output Buffer
Document Revision History
LVPECL
Input Buffer
5-43
Z 0 = 50 Ω
100 Ω
Z 0 = 50 Ω
Document Revision History
Date
January 2014
June 2013
May 2013
January 2013
I/O Features in Stratix V Devices
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Version
2014.01.10
2013.06.21
2013.05.06
2013.01.22
Changes
? Updated statements in several topics to clarify that each modular I/O
bank can support multiple I/O standards that use the same voltages.
? Updated the guideline topic about using the same V CCPD for I/O banks
in the same V CCPD group to improve clarity.
? Clarified that you can only use R D OCT if V CCPD is 2.5 V.
? Corrected the topic about LVDS, RSDS, and Mini-LVDS termination
to remove the requirement of 2.5 V V CCIO . Only V CCPD of 2.5 V is
required for using R D OCT.
? Removed all "preliminary" marks.
? Updated the topic about LVDS input R D OCT to remove the require-
ment for setting the V CCIO to 2.5 V. R D OCT now requires only that the
V CCPD is 2.5 V.
? Updated the topic about LVPECL termination to improve clarity.
? Moved all links to the Related Information section of respective topics
for easy reference.
? Added link to the known document issues in the Knowledge Base.
? Removed all references to column and row I/Os. Stratix V devices have
I/O banks on the top and bottom only.
? Corrected the guideline about using the same V CCPD for all I/O banks
in a group.
? Removed references to LVDS single-ended output with single-resistor
network (LVDS_E_1R). The Stratix V devices do not support LVDS_
E_1R.
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